In the prior art bit clock recovery circuit disclosed in published West German Patent Application AS 24 35 687 a clock generator at the receiving end generates a reference clock whose frequency is N times the frequency of the bit clock, a counter operating as a frequency divider and having at least N count states is cyclically incremented by the reference clock so as to divide the reference clock to the frequency of the bit clock, which is delivered at one of its outputs, the period of the bit clock is divided into N equal portions of time, and the effective pulse edge of the bit clock provided at the output of the counter occurs at the count determined by N/2.
The frequency of the clock generator is n times the frequency of the received bit clock, and the counter is controlled by the logic circuit and synchronously with the pulses from the clock generator in such a way as to be incremented either not at all or by one or two counts depending on the deviation from the desired position. In the synchronous case, an effective pulse edge of the bit clock occurs at the center of each bit unit of the received signal.
Such prior art circuits generate a bit-clock signal whose phase is derived from the beginning, i.e., a leading edge, of a received pulse of the communication signal. Because of the commonly used transmission codes (e.g., HDB3, AMI) and the nonideal characteristics of the transmission lines, the duration of the received pulses may differ from the desired value.
This means that the leading edge of the received pulse of a bit sequence occurs earlier or later, which inevitably leads to continuous phase corrections that counteract a frequency drift for a short time and may thus lead to a higher bit-error rate.